I am a PhD Student at Concurrency and Parallelism Laboratory, KAIST School of Computing. I am working with Prof. Jeehoon Kang on hardware accelerators.
- Computer architecture
- FPGA design and verification
- AI hardware accelerators
- Dynamically reconfigurable processors
- Email: email@example.com
- GitHub: haroonrl
- Bibliography: DBLP, Google Scholar
- Place: Rm. 4441, Bldg. E3-1, KAIST (+82-42-350-7878)
(2017) M.E in Electrical Engineering. Southeast University, China.
(2012) B.S in Electronics Engineering. Sarhad University, Pakistan.
Hardware Engineer, Sahil Semiconductors, December, 2020 - March, 2021.
(topic: ASIC design and verification)
FPGA Design Engineer, Simmir Vision (Shanghai) CO., Ltd., January, 2019 - July, 2021.
(topic: FPGA Enabled-AI Cameras)
(ISCAS 2018) A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration.
IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy.
Awards and Honors
- Fully-funded graduate fellowship,China. (2015-2017)
- KAIST graduate scholarship.(2021-present)