Minseong Jang (장민성)

I am a Ph.D Student at KAIST School of Computing at Concurrency and Parallelism Laboratory.

I am currently working on designing high-level hardware description language

Contact

• Email: minseong.jang@kaist.ac.kr
• GitHub: minseongg
• Bibliography: ORCID, DBLP, Google Scholar
• Place: Rm. 4441, Bldg. E3-1, KAIST (+82-42-350-7878)

Education

• (2024 - Current) Ph.D. in Computer Science. KAIST.

• (2024) M.S. in Computer Science. KAIST.

• (2022) B.S. in Mathematical Sciences & Computer Science. KAIST.

Publications

• (PLDI 2024) Modular Hardware Design of Pipelined Circuits with Hazards.
  Minseong Jang, Jung In Rhee, Woojin Lee, Shuangshuang Zhao, Jeehoon Kang.
  ACM SIGPLAN conference on Programming Languages Design and Implementation.
  [paper: doi, local] ​ ​ ​
  

• (ASPLOS 2023) ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators.
  Sungsoo Han†, Minseong Jang†, Jeehoon Kang (†: co-first authors in alphabetical order).
  The International Conference on Architectural Support for Programming Languages and Operating Systems.
  [paper: doi, local] ​ [artifact: development] ​ ​
  

Experiences

• Software Engineer, Waddle Corporation, April, 2019 - January, 2021.

  (topic: Back-end development, R&D)