Minseong Jang (장민성)
I am a Master Student at KAIST School of Computing at Concurrency and Parallelism Laboratory.
I am currently working on designing high-level hardware description language
Contact
- Email: minseong.jang@kaist.ac.kr
- GitHub: minseongg
- Bibliography: ORCID, DBLP, Google Scholar
- Place: Rm. 4441, Bldg. E3-1, KAIST (+82-42-350-7878)
Education
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(2024) M.S. in Computer Science. KAIST (expected).
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(2022) B.S. in Mathematical Sciences & Computer Science. KAIST.
Publications
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(PLDI 2024)
Modular Hardware Design of Pipelined Circuits with Hazards.
Minseong Jang, Jung In Rhee, Woojin Lee, Shuangshuang Zhao, Jeehoon Kang.
ACM SIGPLAN conference on Programming Languages Design and Implementation (to appear).
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(ASPLOS 2023)
ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators.
Sungsoo Han†, Minseong Jang†, Jeehoon Kang (†: co-first authors in alphabetical order).
The International Conference on Architectural Support for Programming Languages and Operating Systems.
[paper: doi, local] [artifact: development]
Experiences
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Software Engineer, Waddle Corporation, April, 2019 - January, 2021.
(topic: Back-end development, R&D)